1. Field of the Invention
The present invention relates to a semiconductor device and a method of using the same, and in particular to a semiconductor device used in a breakdown-resistive integrated circuit or a power integrated circuit as well as a method of using the same.
2. Description of the Background Art
FIG. 13 is a cross section showing an output element used in a breakdown-resistive IC (Integrated Circuit) or a power IC in the prior art. FIG. 14 is an equivalent circuit diagram of the element shown in FIG. 13. Referring to FIG. 13, the conventional output element used in the breakdown-resistive IC or power IC, an insulating film 3 is formed on a main surface of a semiconductor substrate 1. An n.sup.- -SOI (Silicon On Insulator) layer 2 is formed on insulating film 3. At the main surface of n.sup.- -SOI layer 2, there are formed p-diffusion regions 4, 6 and 5 with a predetermined space between each other. An n.sup.+ -diffusion region 7 is formed at the main surface of p-diffusion region 4. A gate electrode 11 is formed on the main surface of n.sup.- -SOI layer 2 located between p-diffusion regions 4 and 6 with an insulating film 9 therebetween.
An insulating film 20 is formed on n.sup.- -SOI layer 2, and contact holes are formed at predetermined regions in insulating film 20. There is formed a cathode electrode 13 having a portion located in the contact hole of insulating layer 20 and being in contact with the main surface of n.sup.+ -diffusion region 7. There is also formed an electrode 21 having a portion located in the contact hole of insulating layer 20 and being in contact with the main surface of p-diffusion region 6. There is further formed an anode electrode 15 having a portion located in the contact hole of insulating layer 20 and being in contact with the main surface of p-diffusion region 5. Cathode electrode 13 and electrode 21 are electrically connected together via a resistance 17. An electrode 14 is formed on a rear surface of semiconductor substrate 1.
Referring to FIGS. 13 and 14, there is formed an npn bipolar transistor, in which n.sup.+ -diffusion region 7 forms an emitter, p-diffusion region 4 forms a base and n.sup.- -SOI layer 2 forms a collector. There is also formed a pnp bipolar transistor of a multi-collector type, in which p-diffusion region 5 forms an emitter, n.sup.- -SOI layer 2 forms a base and p-diffusion regions 4 and 6 form collectors. In this pnp bipolar transistor including two collectors, the collector (p-diffusion region 6) nearer to the emitter, i.e., p-diffusion region 5 has a larger base transport factor .alpha. than the other.
There is further provided an MOS11 formed of an n-channel MOS transistor, in which n.sup.+ -diffusion region 7 forms a source region, p-diffusion region 4 forms a back gate and n.sup.- -SOI layer 2 forms a drain region. There is also provided an MOS12 formed of a p-channel MOS transistor 12, in which p-diffusion region 6 forms a source region, n.sup.- -SOI layer 2 forms a back gate and p-diffusion region 4 forms a drain region.
Referring to FIGS. 15-17, operation of the conventional semiconductor device shown in FIG. 13 will be described below. First, 0 V is applied to cathode electrode 13 and electrode 14, -Vg is applied to gate electrode 11 and +Vd is applied to anode electrode 15. Thereby, as shown in FIG. 15, a surface portion of n.sup.- -SOI layer 2 located under gate electrode 11 is inverted into the p-type. This results in short-circuit between p-diffusion region 4 and n.sup.+ -diffusion region 7, so that this output element is turned off.
In this state, as shown in FIG. 16, the voltage applied to gate electrode 11 is changed into +Vg. Thereby, the surface of p-diffusion region 4 is inverted into the n-type, so that an electron current flows from n.sup.+ -diffusion region 7 into n.sup.- -SOI layer 2. As the electron current flows into p-diffusion region 5, a hole current flows from p-diffusion region 5 into n.sup.- -SOI layer 2. This hole current forms a base current of the npn bipolar transistor, resulting in thyristor operation.
In order to turn off the thyristor operation described in connection with FIG. 16, the voltage applied to gate electrode 11 is set to -Vg again as shown in FIG. 17. Thereby, the surface of n.sup.- -SOI layer 2 under gate electrode 11 is inverted into the p-type, so that the hole current flowed into p-diffusion region 4 flows into p-diffusion region 6. At the same time, the hole current in n.sup.- -SOI layer 2 is pulled out via p-diffusion region 6, so that the base current of npn bipolar transistor decreases. Thereby, the thyristor operation is turned off.
In the conventional semiconductor device shown in FIG. 13, if the resistance 17 has a large resistance value, only a reduced amount of hole current flows from p-diffusion region 4 into p-diffusion region 6 during the turning off shown in FIG. 17, which results in such a disadvantage that the base current of npn bipolar transistor cannot be reduced sufficiently. Thereby, such a problem arises that the thyristor operation of npn bipolar transistor cannot be turned off in an intended manner. Meanwhile, if the resistance value of resistance 17 is set to, e.g., 0 V, the maximum controllable current increases because a large hole current flows from p-diffusion region 4 to p-diffusion region 6 during the turning off. In this case, however, a large hole current flows from p-diffusion region 6 to cathode electrode 13 in the on state, so that a base current of the npn bipolar transistor disadvantageously decreases. This results in such a problem that a holding current in the thyristor operation increases.
In the conventional semiconductor device, if p-channel MOS12 including p-diffusion regions 4 and 6 as well as gate electrode 11 has a small channel length (gate length), a resistance is generated by a JFET effect against n-channel MOS11 including n.sup.+ -diffusion region 7, n.sup.- -SOI layer 2 and gate electrode 11. For this reason, MOS12 actually has a relatively long channel length (gate length) in the conventional device. As a result, MOS12 has a large on-resistance in the prior art, and thus, the maximum controllable current is disadvantageously small.